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HT-9464 High Voltage Tester
Commander 2000 High Speed Pick and Place Handler
Commander Accelerator-100 High Speed Programmer
   

Products > Commander accelerator-100 high speed programmer

Commander Accelerator-100 High Speed Programmer



Introduction

The Commander High Speed Programmer (HSP) is low overhead system designed to test Flash Memories, PLA's and Micro-controllers.

The parallel multi-module architecture provides the flexibility to program and test multiple devices. It's full-featured capabilities support chip erasing and programming, sector erasing and programming, sector protect and unprotect, and data verification functions.

The HSP can be used as a stand-alone system or, if required, integrated into the Commander handler to test up to 16 devices in parallel. The system consists of a supervisory module and a programming mainframe bay. The system supervisory module consists of a system supervisory computer, monitor, keyboard and mouse. The programming mainframe consists of the programming modules, power supplies and LAN facilities.


HSP Specifications

Pin Electronics Power supply
Vin
Range 0 to 6.375 volts
Iin 50ma
Resolution 5mv
Accuracy 25mv
Vhh1
Range 0 to +12v
Ihh1 20ma
Resolution 10mv
Accuracy 50mv
Vhh2
Range 0 to +12v
Ihh2 20ma
Resolution 10mv
Accuracy 50mv
Vhh3
Range 0 to +12v
Ihh3 20ma
Resolution 10mv
Accuracy 50mv
Vil
Range Ground
V0
Range 0 to +5v
Resolution 5mv
Accuracy 25mv
DUT Protection
Current clamp
Icc 50ma to 250 ma programmable
Ipp 25ma to 125 ma programmable.
Voltage clamp
Vcc 1 to 6.375 V programmable
Vpp 1 to 12 V programmable
Current Limiting All signal pins
Over voltage protection All signal pins
Pin Driver
Max data rate 10MHz
DQ D0 toD7
Vih to Vil A0 to A23
Control Lines Vhh1, Vhh2, Vhh3 or Vih to Vil
Driver accuracy +/- 100mv
Driver output AC impedance 50 Ohm typical
Programming Algorithm
  • Auto device identification
  • Auto device socket contact check
  • Blank check
  • Programming
  • Verification
  • Sector device erasure
  • Sector device protection
  • Embedded algorithms
  • JTAG algorithms
  • Conventional programming algorithms
5.0 Throughput
  • Less than 10%
  • Program overhead in unlock mode
  • True Parallel test system architecture
  • Supports fast embedded algorithms
  • Zero device idling time, limited only by speed of the handler or device whichever is slower
Erase pulse
Range 0 to 200 Micro-seconds
Resolution 0 to 200 Micro-seconds
Address Field
  24 bit; A0 to A23
Data field
  16 bit; DQ0 to DQ7, DQ8 to DQ14,
and DQ15/A-1
Control Field
  8 Bit: CE/, OE/, WE/, BYTE/, RESET/, and CT0:2
Command Field
  8 it; DQ0:7
Status Field
  9 Bits: DQ0 to DQ7 and RY/BZ/
DUT Power Supply
  Vcc
Range 0 to 6.375 Volts
Icc
Resolution 250ma
Accuracy 25mv
Vff
Range 0 to +12 Volts
Accuracy 125ma
Iff 125ma
Resolution 10mv
Accuracy 50mv
Pin Comparator
Input Impedance 10K + 100 pf
Accuracy +/- 100mv
System Programming
Support
  • Windows based platform
  • Flexible Menu
  • Device batch number/control
  • Algorithm downloading capability
  • Local algorithmic file storage capability
  • Socket alarm and lock out capability
  • Binning support
  • Manual interactive mode
Device package
Support All package types such as PLCC, QFP, SOIC, TSOP, BGA

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